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smsc ds ? PPC34C60 rev. 06/01/2001 advanced information parallel port interface chip - peripheral side features creates pc/at-style bus from parallel printer port signals single chip interface to any bus capable peripheral supports standard, bi-d irectional, epp, and ecp parallel ports burst mode for improved data transfer rates adaptive interface optimizes transfer rates to parallel port characteristics digital signal filtering increases noise immunity allows daisy-chain of up to eight peripherals including standard printer provides interrupt sharing with daisy-chained devices 16-bit product id support peripheral bus clock selectable at system clock /2, /3, /5, or /6 interfaces to 8-bit and/or 16-bit peripherals fifo operation permits overlapping parallel port and peripheral bus cycles for maximum data transfer rate flexible dram buffer support and dma capability four output lines individually configurable as chip selects or general purpose outputs three output lines individually configurable as strobes or general purpose outputs four uncommitted inputs watchdog monitors host computer activity low battery detect input direct output for piezo transducer support for automatic power up/down prevents host system latchup with powerback control on chip crystal oscillator general description the PPC34C60 provides a means of re-gener ating an ibm at style (isa) bus from t he pc printer port signals. in addition to standard (compatible) printer ports, t he PPC34C60 supports ps/2 (bi-directional ), epp, and ecp ports. up to eight peripherals may be daisy chained between the computer and the printer. printer operation is unaffected. the PPC34C60 performs as an intelligent data mux. it mult iplexes the printer port signals between the daisy chain (pass-through) outputs and there- generated isa bus. furthermore, it handles break ing up 8- and 16-bit isa data into 4- or 8-bit chunks for the parallel port. the PPC34C60 also provides a piezo transduc er driver for battery-powered systems. the transducer will signal low battery with two repeated beeps. if the cable to the computer is disc onnected, or if the host is dor mant for about a minute, the transducer will signal inactivity with four beeps. additionally, a power-down signal can be provided to external circuitry to automatically shut down system power during inactivity. PPC34C60
smsc ds ? PPC34C60 page 2 rev. 06/01/2001 advanced information 80 arkay drive hauppauge, ny 11788 (631) 435-6000 fax (631) 273-3123 copyright ? smsc 2004. all rights reserved. circuit diagrams and other information rela ting to smsc products are included as a m eans of illustrating typical applications. consequently, complete information sufficient for c onstruction purposes is not necessarily given. although the information has been checked and is bel ieved to be accurate, no responsibility is assumed for inaccuracies. smsc reserves the right to make changes to specifications and product descriptions at any time without notice. contact your local smsc sales office to obtain the la test specifications before placi ng your product order. the provisi on of this information does not convey to the purchaser of the described semiconductor devic es any licenses under any patent ri ghts or other intellectual p roperty rights of smsc or others. all sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of smsc's standard terms of sale agreement dated before the date of your order (t he "terms of sale agreement"). the product may contain design def ects or errors known as anomalies which may caus e the product's functions to deviate from publis hed specifications. anomaly sheets are availab le upon request. smsc products are not designed, intended, authorized or warranted for use in any life support or other application where produc t failure could cause or contribute to personal injury or severe property damage. any and all such uses without prior written approval of an officer of smsc and further testing and/or modification will be fully at t he risk of the customer. copies of this do cument or other smsc literature, as wel l as the terms of sale agreement, may be obtained by visiting smsc?s website at http://www .smsc.com. smsc is a registered trademark of standard micros ystems corporation (?smsc?). product names and company names are the trademarks of their respective holders. smsc disclaims and excludes any and a ll warranties, including without limitation any and all implied warranties of merchantability, fitn ess for a particular purpose, title, and against infringement and the like, and any and all warranties arising from any course of dealing or usage of trade. in no event shall smsc be liable for an y direct, incidental , indirect, special, punitive, or consequential damages; or for lost data, profits, savings or revenues of any kind; regardless of th e form of action, whether based on contract; tort; negligence of smsc or others; strict li ability; breach of warranty; or otherwise; whether or not any remedy of buyer is held to have failed of its essential purpose, and whet her or not smsc has been advised of the possibility of such damages.
smsc ds ? PPC34C60 page 3 rev. 06/01/2001 advanced information table of contents 1 pin conf iguration ............................................................................................................ ..............................4 1.1 buffer type descriptions................................................................................................... ........................11 1.2 general conventions ........................................................................................................ .........................11 1.3 reference docume nts ........................................................................................................ .......................11 2 PPC34C60 blo ck descri ption ................................................................................................... .................12 3 daisy chain co mmand protocol................................................................................................. ............13 3.1 peripheral s ystem d esign ................................................................................................... ......................14 3.2 design example ............................................................................................................. ............................15 3.3 device addressing .......................................................................................................... ...........................16 3.4 internal re gister map...................................................................................................... ...........................18 4 register d escript ions ........................................................................................................ .......................19 5 dram buffe r operation........................................................................................................ .....................29 5.1 dram physica l addressing................................................................................................... .....................30 6 system data bus cy cles ....................................................................................................... ....................31 7 operational descript ion...................................................................................................... ....................34 8 timing diagrams .............................................................................................................. ..............................36 8.1 dma transfer cycle timing .................................................................................................. ....................57
smsc ds ? PPC34C60 page 4 rev. 06/01/2001 advanced information 1 pin configuration 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 npid slctd irq dreq tc ndack nst0 nst1 nst2 vcc gnd nwdogen piezo in2 in3 nlbat nreset sense yin yout nio16 in0 in1 ncs0 ncs1 ncs2 ncs3 nsrd nswr vcc gnd nras ncas nsrst srst xin(sclk) xout bclk n/c test sd0 sd15 sd14 sd13 sd12 sd11 sd10 sd9 sd8 gnd vcc sd7 sd6 sd5 sd4 sd3 sd2 sd1 ma9 ma8 gnd vcc sa7 sa6 sa4 sa3 sa2 sa1 sa0 sa5 PPC34C60 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 hslct npstb hpe npalf hbsy nperr nhack npinit gnd vcc hd7 hd5 hd4 hd3 nhsel hd2 npack nhinit gnd vcc hd1 pbsy hd0 ppe nhalf nhstb nherr pslct hd6 npsel 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
smsc ds ? PPC34C60 page 5 rev. 06/01/2001 advanced information description of pin functions pin no. name symbol buffer type description parallel port host control and common data bus interface 2 nhost:strobe nhstb i,pu an active low pulse on this input is used to strobe printer data into the printer. refer to section 4 of the ieee std 1284 (reference 1) for use of this pin in ecp and epp modes. 3 nhost:auto line feed nhalf i,pu this input goes low to cause the printer to automatically feed one line after each line is printed. connects to autofd output from host. refer to section 4 of the ieee std 1284 (reference 1) for use of this pin in ecp and epp modes. 14 nhost:selectin nhsel i this active low input is driven by the host to select the printer. connects to select in output from host. refer to section 4 of the ieee std 1284 (reference 1) for use of this pin in ecp and epp modes. (see note 1 on page 11.) 11 nhost:initiate nhinit i this active low input initiates the printer when low. connects to init output from host. refer to section 4 of the ieee std 1284 (reference 1) for use of this pin in ecp and epp modes. (see note 1 on page 11.) 24 nhost: acknowledge nhack o16 this active low output from the printer is used to indicate that the printer has received the data and is ready to accept new data. connects to the ack input to the host. refer to section 4 of the ieee std 1284 (reference 1) for use of this pin in ecp and epp modes. 26 host:busy hbsy o16 this status output, generated by the printer, goes high to indi cate that it is not ready to receive new data from the host. connects to the busy input to the host. refer to section 4 of the ieee std 1284 (reference 1) for use of this pin in ecp and epp modes. 28 host:paper end hpe o16 this status output, generated by the printer, goes high to indicate that the printer is out of paper. connects to the perror input to the host. refer to section 4 of the ieee std 1284 (reference 1) for use of this pin in ecp and epp modes.
smsc ds ? PPC34C60 page 6 rev. 06/01/2001 advanced information description of pin functions pin no. name symbol buffer type description 30 host:printer selected hslct o16 this status output, generated by the printer, goes high to indicate that the printer is selected. connects to the select input to the host. refer to section 4 of the ieee std 1284 (reference 1) for use of this pin in ecp and epp modes. 6 nhost:printer error nherr o16 this status output, generated by the printer, goes low to indicate an error condition at the printer. connects to the error input to the host. refer to section 4 of the ieee std 1284 (reference 1) for use of this pin in ecp and epp modes. 5,8,13,15 -18, 20 host:data[0:7] hd[0:7] i/o16, pu parallel port bi-directional data bus connected to host system is used by spp, ecp and epp to transfer data between the host cpu and peripherals. refer to section 4 of the ieee std 1284 (reference 1) for use of this pin in ecp and epp modes. parallel port pass-through interface pins 29 npass-through: strobe npstb o16 an active low pulse on this output is used to strobe printer data into the printer. connects to the strobe input on the next device along the chain. refer to section 4 of the ieee std 1284 (reference 1) for use of this pin in ecp and epp modes. 27 npass-through: auto line feed npalf o16 this output goes low to cause the printer to automatically feed one line after each line is printed. connects to the autofd input on the next devic e along the chain. refer to section 4 of the ieee std 1284 (reference 1) for use of this pin in ecp and epp modes.
smsc ds ? PPC34C60 page 7 rev. 06/01/2001 advanced information description of pin functions pin no. name symbol buffer type description 19 npass-through: selectin npsel o16 this active low output selects the printer. connects to the select in input on the next device along the chain. refer to section 4 of the ieee std 1284 (reference 1) for use of this pin in ecp and epp modes. 23 npass-through: initiate npinit o16 this active low output initiates the printer when low. connects to the init input on the next device along the chain. refer to section 4 of the ieee std 1284 (reference 1) for use of this pin in ecp and epp modes. 12 npass-through: acknowledge npack i, pu this active low input from the printer is used to indicate that the printer has received the data and is ready to accept new data. connects to the ack output from the next device along the chain. refer to section 4 of the ieee std 1284 (reference 1) for use of this pin in ecp and epp modes. 7 pass-through: busy pbsy i, pu this status input, generated by the printer goes high to indicate that it is not ready to receive new data from the pass-through. connects to the busy output from the next device along the chain. refer to section 4 of the ieee std 1284 (reference 1) for use of this pin in ecp/epp modes. 4 pass-through: paper end ppe i, pu this status input, generated by the printer, goes high to indicate that the printer is out of paper. connects to the perror output from the next device along the chain. refer to section 4 of the ieee std 1284 (reference 1) for use of this pin in ecp and epp modes. 1 pass-through: printer selected pslct i, pu this status input, generated by the printer, goes high to indicate that the printer is selected. connects to the select output from the next device along the chain. refer to section 4 of the ieee std 1284 (reference 1) for use of this pin in ecp/epp modes. 25 npass-through: printer error nperr i, pu this status output, generated by the printer, goes low to indicate an error condition at the printer. connects to the error output from the next device along the chain. refer to section 4 of the ieee std 1284 (reference 1) for use of this pin in ecp and epp modes.
smsc ds ? PPC34C60 page 8 rev. 06/01/2001 advanced information description of pin functions pin no. name symbol buffer type description system (regenerated isa peripheral) interface 96 97 system clock/crystal xin (sclk) xout i o8 xin may be connected to a ttl peripheral system clock or a crystal may be placed across xin/xout (t ypically 24mhz). this is used to derive the internal clock (busclk) used for all system interface timing. 80-73 system address [0:7] sa[0:7] o8 these lower eight address bits are presented to the system bus directly by the PPC34C60 during bus and dram access. upper addr ess bits, if needed, should be latched through use of the PPC34C60's strobe lines prior to generating bus accesses. 70,69 memory address [8,9] ma[8:9] o8 these address bits are appended to sa[0:7] to create a 10-bit row or column address for dram access. 68-61, 58-51 system data [0:15] sd[0:15] i/o8, pu these bi-directional pins are used to transfer data during bus or dram cycles to or from the system. 88 nsystem read nsrd o8 this indicates that a bus read cycle is occurring, similar to an isa memr signal. 89 nsystem write nswr o8 this indicates that a bus write cycle is occurring, similar to an isa memw signal. 81 n16-bit i/o nio16 i, pu this signal is asserted by the remote system to indicate whether or not the address being accessed is capable of a 16-bit transfer. 48 interrupt request irq i, pu this rising edge activated signal indicates an interrupt request from the system. 94 nsystem reset nsrst o8 this low going signal can be used to reset the system. this signal is asserted for 16 sclks. 95 system reset srst o8 this high going signal can be used to reset the system. this signal is asserted for 16 sclks. 92 nrow address strobe nras o8 this low going strobe signal is used by the dram to latch the row address, present on the sa[0:7] and ma[8:9] pins. this output drives the dram directly, however a series resistor is recommended on this line. 93 ncolumn address strobe ncas o8 this low going strobe signal is used by the dram to latch the column address, present on the sa[0:7] and ma[8:9] pins. this output drives the dram directly, however a series resistor is recommended on this line. 45 ndma acknowledge ndack o8 this active low output signal is issued to inform the system that data is to be transferred using dma transfer cycles.
smsc ds ? PPC34C60 page 9 rev. 06/01/2001 advanced information description of pin functions pin no. name symbol buffer type description 46 terminal count tc o8 this active high output is asserted with the last dma data transfer to indicate to the system that the dma data transfer is complete. tc is asserted in conjunction with dack. 47 dma request dreq i, pd the remote system indicates that it is ready to perform dma transfers by driving this line high. this signal is asserted as long as t he system is ready to receive or send data and is deasserted on the last byte of the data transfer. miscellaneous 39 nwatchdog enable nwdogen i, pu pulling this line low enables the watchdog. the watchdog will generate four beeps on the piezo driver if there are no transitions on the host port lines for a minute. this circuitry can also automatically power down the system when the watchdog "barks". this feature requires software to tickle the port every 30 seconds. 34 nreset chip nreset i, pu pulling this line low for two sysclks will reset the PPC34C60 to its initial state. this will reset all internal registers to their default values. 35 nlow battery indicator nlbat i, pu a low level on this input line signals that the battery power is low and the PPC34C60 will generate low battery tones. it is the responsibility of the remote system to monitor battery power and generate this input signal. 82,83, 37,36 general purpose inputs [0:3] in[0:3] i, pu the host may obtain the level at these pins by reading the internal input register. 38 piezo crystal drive piezo o24 this high current output can be directly hooked up to a piezo speaker to provide audio tones. 44,43, 42 nstrobes[0:2] (special function) nst[0:2] o8 these pins are individually configured as general purpose outputs or as strobe outputs as programmed in the output configuration register. st2 may also be programmed as the auto-power pin. 84-87 nchip selects[0:3] (special function) ncs[0:3] o8 these pins are individually configured as general purpose outputs or as chip select outputs as programmed in the output configuration register. 32 31 oscillator input oscillator output yin yout i 08 a parallel resonant crystal or rc network may be placed across yin and yout. this nominal 32khz clock (32.768khz) is used by the internal piezo driver and watchdog timer.
smsc ds ? PPC34C60 page 10 rev. 06/01/2001 advanced information description of pin functions pin no. name symbol buffer type description 49 selected device slctd o8 this signal is an active high output that indicates that the device is the active device on the daisy chain. this may be used for debug purposes, to enable drivers, or to qualify signals. 50 nproduct id pid o8 this signal is an active low output asserted when the host performs a request for the peripheral's product id. this function is used by the daisy chain and multiplexor protocols. 33 sense vcc sense i, pd when pulled high, this input will enable all output drivers of the PPC34C60. when low, all outputs are tri-stated. this resolves the back-power problem inherent in parallel port peripherals. isolate the chip's vcc from the rest of the peripheral's vcc using a schottky diode. the sense input should be tied to the peripheral's vcc and the anode of the diode. in this manner, when the peripheral's power is off, the sense input will shut down all out puts, preventing the chip from driving into a low impedance load and consequently damaging the chip's input protection diodes. 100 test counters test i, pd this is an active high signal that allows access to some large counter chains that are normally buried within the chip. for normal operation this input should be left unconnected, or tied to ground. for more information on the test mode contact the factory. 98 busclk bclk o8 busclk is the sclk divided by the value programmed in the configuration register. 99 reserved reserved leave floating, no connection 9,21, 41,60, 72,90 power vcc +5 volt supply pins. 10,22, 40,59, 71,91 ground gnd ground pins note 1: by pulling both these lines low (illegal state) , the PPC34C60's output ports can be disabled.
smsc ds ? PPC34C60 page 11 rev. 06/01/2001 advanced information 1.1 buffer type descriptions buffer type description i i/o8 i/o16 o8 o16 o24 pu pd input, schmitt trigger input, schmitt trigger/8ma output input, schmitt trigger/16ma output 8ma output 16ma output 24ma output pull up, nominal 100k pull down, nominal 100k 1.2 general conventions throughout this document, the following va rious terms and conventions will be used: compatible = "centronics" spp = "standard bi-directional parallel port" (ps/2) epp = "enhanced parallel port" ecp = "extended capabilities port" 1.3 reference documents ieee std 1284, february 2, 1993. the enhanced parallel port, an introduc tion; farpoint communications. daisy chain specification, rev. 1.1, september 16, 1993; disctec corporation. enhanced parallel port bios specification, rev 3, february 12, 1993; farpoint communications. ecp: specification kit, rev 1.03, febr uary 10, 1993; microsoft corporation.
smsc ds ? PPC34C60 page 12 rev. 06/01/2001 advanced information 2 PPC34C60 block description the PPC34C60 can be broken down into eight functional blocks as shown in figure 1. the PPC34C60 implements and complies with the daisy chai n specification (reference 3) through the daisy chain protocol block. under the daisy ch ain protocol, the PPC34C60 operates in either pass-through or selected mode. pass-through mode is the power up default, and is electrically transparent to devic es further down the chain. when in pass-through mode, the data sw itch gates the control and status lines of the parallel port to the pass-through port. selected mode connects the system interfac e bus to the parallel port. when in selected mode, the data switch gates the control and status lines to the PPC34C60's protocol translator functional block. the protocol translator block gives the PPC34C60 its capability to communicate with the parallel port in either spp, epp, or ecp mode. the protocol translator inte rprets the multiport access protocol (ma p) packets described in the daisy chain specification (reference 3). the map packets and command c odes are described in the dais y chain command protocol. the protocol translator also decodes t he type of parallel port transfer (ie. address write/data read_write cycle) and provides the proper control of the data to the registers and control block a nd to the bus interface block. the PPC34C60's internal registers, contained in the regist er and control block, control the operation of the chip's internal dram controller, dma controller, and watchdog controller. the bus interface bl ock controls data transfers between the parallel port and the peripheral's system interface bus. the mux block routes data and cont rol signals to the system interface. figure 1 - internal block diagram daisy chain protocol data switch protocol translator spp epp ecp a_stb b_stb registers and control bus interface dram c ontrolle r dma c ontrolle r wdog & piezo counters mux system interface speaker host parallel port pass-through port nhstb nhalf nhsel nhinit nhack hbsy hpe hslct nherr hd[0:7] npstb npalf npsel npinit npack pbsy ppe pslct nperr hd[0:7] slctd nreset sense test ndack tc dreq nras ncas ndir npid in[0:3] nst[0:2] ncs[0:3] srst nsrst sa[0:7] ma[8:9] sd[0:15] nsrd nswr nio16 irq xin, xout yin, yout, nwdogen, piezo nlbat
smsc ds ? PPC34C60 page 13 rev. 06/01/2001 advanced information 3 daisy chain command protocol the daisy chain protocol is used to se lect the mode of each device and to allow connection of up to eight devices on one parallel port. the daisy chain commands use the multiport access pr otocol (map) to access the devices. the format of the map packets is as follows: the command byte in the map packet represents a code and po ssibly an address as well. the currently defined codes are: (00-07) (08-0f) (10-17) (20-27) (30) (40) (48) (50-57) (58-5f) (d0-d7) (e0-e7) 0000 0aaa 0000 1aaa 0001 0aaa 0010 0aaa 0011 xxxx 0100 0xxx 0100 1xxx 0101 0aaa 0101 1aaa 1101 0aaa 1110 0aaa assign address aaa to the current device query interrupt from device aaa query product id from device aaa select device aaa in epp mode de-select all devices disable daisy chain interrupts enable daisy chain interrupts clear interrupt latches on device aaa set interrupt latch on device aaa select device aaa in ecp mode select device aaa in compatible mode - spp aaa = device address xxx = undefined - set to zero refer to the daisy chain specification (reference 3) for more information.
smsc ds ? PPC34C60 page 14 rev. 06/01/2001 advanced information 3.1 peripheral system design the PPC34C60 simplifies the design of a peripheral to expl oit the benefits of ieee std 1284, standard signaling for a bi- directional parallel port (reference 1). figure 2 depicts a hi gh-level system block diagram which shows the peripheral chip's three primary data paths. note that the parallel port data bus is not switched through the PPC34C60; this allows all daisy chained devices to receive a special "out of band" control packet as defined in the distec daisy chain s pecification (reference 3). figure 2 - system block diagram npstb npalf npsel npinit npack pbsy ppe pslct nperr nhstb nhalf nhsel nhinit nhack hbsy hpe hslct nherr host parallel port connector pass-through parallel port connector h o s t p o r t p a s s t h r u parallel port data bus PPC34C60 system interface isa peripheral
smsc ds ? PPC34C60 page 15 rev. 06/01/2001 advanced information 3.2 design example figure 3 shows a simple system design t hat uses most of the PPC34C60's interf ace functions. this example shows: 1) a dram interface. 2) an 8kx8 nv-memory device interface using nstrobe output 0 to latch the upper address bits and nchip select output 0 to enable the device. 3) an interface to smsc's fdc37c662 s uper i/o floppy disk controller. this se ction of the design illustrates how the PPC34C60 can handle a direct memory access interface, f our interrupts, and an additional chip select output configured as a standard output pin. the srst (reset output) is used to reset the floppy disk controller. 4) the use of 10k bias resistors to implement a product id code. figure 3 - typical system interface PPC34C60 a[8:9] a[0:7] nwr noe nras ncas sd[0:7] a[8:9] a[0:7] nwr noe nras ncas sd[8:15] 1mx8 dram 1mx8 dram 374 d[0:7] q[0:7] clock noe a[0:7] a[8:12] nwr noe sd[0:7] optional, 8kx8 sram eeprom, etc. fdc37c662 d[0:7] a[0:7] a[8:9] niow nior fdrq ndack tc irq3 irq4 pintr fintr aen rst sd[0:15] ma[8:9] sa[0:7] nswr nsrd nras ncas nio16 nst0 nce ncs0 dreq ndack tc in0 in1 in2 in3 cs1 srst irq upper address latch test xin xout yin yo u t 24mhz 32 khz npid npid sd0 sd5 sd10 sd15 npid product id = 7bdeh
smsc ds ? PPC34C60 page 16 rev. 06/01/2001 advanced information 3.3 device addressing the bi-directional parallel peripheral interface protocol, de fined by the ieee std 1284 (reference 1), describes two basic types of 8-bit information transfers: data read/write operat ions and address read/write operati ons. the PPC34C60's bus and internal registers are accessed via data read/write operations. the PPC34C60's address mode is set through an spp, epp, or ec p address write operation. tabl e 1 specifies the control signals used by each protocol to perform address and data cycl es and to indicate reverse data flow. refer to the ieee std 1284 (reference 1) for further information. table 1 - key address/data cycle signals signal spp epp ecp address strobe sel sel stb(alf=0) data strobe stb alf stb(alf=1) reverse channel signal init=0 implicit init = 0 the parallel port provides a byte-wide parallel data path. figure 4 defines the data bits of this parallel port data path during an address write operation to the PPC34C60. figure 4 - parallel port address write and data bits 1bma waaa d7 d5 d4 d3 d6 d2 d1 d0 bus or register address type of access write/read required for ecp
smsc ds ? PPC34C60 page 17 rev. 06/01/2001 advanced information an address write cycle is used to select the PPC34C60's addr ess mode for subsequent data write cycles. table 2 shows ten types of address modes into which the PPC34C60 may be placed. the address write data byte required for each mode is encoded as '1wbma3a2a1a0'. table 2 also illustrates three separate system data bu s addressing modes along with dram and internal registers addressing. when the host address write data is 1x100xxx, the PPC34C60 provides unrestricted system data bus access for all subsequent host parallel port data exchanges. unrestricted system data bus access can also occur following address write operations where 1wbma3a2a1a0 = 1x00(a3-a0), except that in this short hand addressing mode a3-a0 is also written to the least significant four bits of the PPC34C60 internal address register. address write operatio ns where 1wbma3a2a1a0 = 1x01(a3-a0) provides block count limited system data bus access with shorthand addressing. for example, an address write operation in which b = 1, m = 0, and a3a2a1a0 = 0000 selects system data bus access but does not alter the value of the PPC34C60 address bus, sa[0:7]. table 2 - address mode operations 1wbm a3a2a1a0 access type w=1(write) w=0(read) 1x00 (a3-a0) system data bus unrestricted bus write (shorthand mode) unrestricted bus read (shorthand mode) 1x01 (a3-a0) block restricted bus write (shorthand mode) block restricted bus read (shorthand mode) 1x10 0xxx (bus) unrestricted bus write access unrestricted bus read access 1x10 1xxx (dram) dram dram write acce ss dram read access 1x11 rrrr internal registers write internal register rrrr read internal register rrrr w = write b = bus m = max count a3a2a1a0 = address selector rrrr = register selector
smsc ds ? PPC34C60 page 18 rev. 06/01/2001 advanced information 3.4 internal register map the internal registers of the PPC34C60 are selected by performing an address write cycle with bits b and m (bits 5 and 4) set to 1,1 (see table 2). the desired register is select ed by the binary value of a3a2a1a0 (bits-3:0), also shown as rrrr. internal register rrrr is made available for read or writ e based on the bit value of w (bit 6) as shown below. all internal registers are eight bits wide. table 3 - internal register map w* bm rrrr register description defaults x 11 0000 address register 00 x 11 0001 output configuration reg 10 x 11 0010 output register 80 1 11 0011 sound register na 0 11 0011 input register sf x 11 0100 operation register 00 x 11 0101 dram buffer size register 0c x 11 0110 host dram buffer pointer 00 x 11 0111 dma dram buffer pointer 00 x 11 1000 host max block count - low 00 x 11 1001 host max block count - high 10 x 11 1010 dma byte count - low 00 x 11 1011 dma byte count - high 00 x 11 1100 configuration register 04 0 11 1101 chip revision level 00 1 11 1110 port test register na 0 11 1110 port test register 00 x 11 1111 data transfer control register 01 *w x = read/write 1 = write 0 = read
smsc ds ? PPC34C60 page 19 rev. 06/01/2001 advanced information 4 register descriptions address register - 0000 (read/write) the value in the address register repres ents the current address presented to the bus address lines sa[0:7]. the primary method of updating this value is the fo llowing sequence. first the address regi ster is selected to be written to by performing an address write operation (x wbma3a2a1a0=x1110000). next a data write operation is issued to write a<0:7> as a group equal to the value presen ted on the parallel port host data lines hd[0:7]. a shorthand mode is also provided to allow the address to be modified and bus operation to be selected in one address write operation. if b = 0, then bus operati on is selected and a3a2a1a0 is written to a<0-3>; a<4-7> are unaffected. in this mode, if m = 1, then the bus acce ss will be limited by the host max block count register. any attempts to read more data will return invalid data. the PPC34C60 contains an inte grated fifo to enhance perform ance by reading the bus one or two bytes ahead of the host port. as an example, some devi ces such as ide hard drives expect data to be read in a fixed block length (sector). set maxcnt (configuration register bit 6) and set the value of host max block count register to the length of the ide data block to read only the des ired amount of data (1 sector) from the peripheral. if m = 0, then the current setting of maxcnt and host ma x block count are ignored. this allows polling of a status register without limiting the number of times the register may be accessed. the PPC34C60 directly provides eight address lines. if more than eight bits of address are necessary, three strobe lines are available which may be used with external circuitry to latc h higher-order address bits off of sa[0:7]. for example, the address register can be written with higher order address bits and latched with one or more of the three programmable strobe lines. the address register is then written with a0-a7, and normal bus reads/writes follow. this scheme may be extended to any size address bus needed. an auto-increment option may be activat ed by setting autoinc (bit 4 in the o peration register, rrrr=0100) which will increment a<0:7> after each bus access.
smsc ds ? PPC34C60 page 20 rev. 06/01/2001 advanced information output configuration register - 0001 (read/write) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sp1 sp0 so1 so0 co3 co2 co1 co0 the output configuration register defines the operation of the bits in the output register. the PPC34C60 has eight independent output lines . the functionality of seven of thes e output lines is selected through the output configuration register. all ei ght output lines are then c ontrolled or activated thr ough the output register (rrrr=0010). the seven programmable output lines controlled by output regi ster bits 0-6 can be selected to operate as either general purpose output pins (inverting), or as s pecial function output pins. the special functions are: chip select, strobe, and auto-power. the eighth (non-programmable) output line is controlled by out put register bit 7. this output line is defined as "bus reset", but it is simply an output bit. it ma y be used for other purposes if a bus re set signal is not required or generated elsewhere. this bit is present on two pins ( 95 and 94) in both normal and inverted polarities. bits 0-3: special functions for programmable output lines 0-3: programmable output lines 0-3 c an be individually configured as general purpos e (inverting) outputs or as chip select outputs. chip selects ar e generated by the bus cy cle state machine. during a bus cycle, the chip select goes low at the star t of the cycle and remains low until the end of the cycle. output line n (n = 0...3) is controlled through output regist er bit n. output line n, configured as a general purpose output, will present the inverted value writt en to output register bit n. output line n, configured as a chip select, will foll ow the bus chip select if outp ut register bit n is a 1. bit 0:co0 - chip select 0/standard output 0 0 select output line 0 (pin 84) as a general purpose inverting output. 1 select output line 0 (pin 84) as a chip select output. bit 1:co1 - chip select 1/standard output 1 0 select output line 1 (pin 85) as a general purpose inverting output. 1 select output line 1 (pin 85) as a chip select output. bit 2:co2 - chip select 2/standard output 2 0 select output line 2 (pin 86) as a general purpose inverting output. 1 select output line 2 (pin 86) as a chip select output. bit 3:co3 - chip select 3/standard output 3 0 select output line 3 (pin 87) as a general purpose inverting output. 1 select output line 3 (pin 87) as a chip select output. bits 4-7: special functions for programmable output lines 4-6 programmable output lines 4-6 can be indi vidually configured as general purpose (i nverting) outputs or as strobe outputs. these strobe signals may be used to clock any edge-triggered flip -flop or register. additionally, programmable output line 6 may be programmed as an auto-power pin. this signal allows a peripheral to automatically control its power on state, so that a separate power switch is not necessary. the external circuitry nec essary for this passively pulls down the init line from the host. the power supply is turned on when the init line rises to a high logic level. the PPC34C60 will then monitor the host, and will bring the auto-power pin to a logic low level when the power can be shut off. output line n, configured as a strobe signal, is normally high and pulses low momentarily when a 1 is written to output register bit n.
smsc ds ? PPC34C60 page 21 rev. 06/01/2001 advanced information bit 4:so0 - strobe 0/standard output 4 0 select output line 4 (pin 44) as a general purpose inverting output. 1 select output line 4 (pin 44) as a strobe output. bit 5:so1 - strobe 1/standard output 5 0 select output line 5 (pin 43) as a general purpose inverting output. 1 select output line 5 (pin 43) as a strobe output. bit 6,7:sp0,sp1 - auto-power/strobe 2/standard output 6 0,x select output line 6 (pin 42) as an auto-power pin. 1,0 select output line 6 (pin 42) as a general purpose inverting output. 1,1 select output line 6 (pin 42) as a strobe output. output register - 0010 (read/write) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 breset nop6 npwr stb2 nop5 stb1 nop4 stb0 nop3 cs3 nop2 cs2 nop1 cs1 nop0 cs0 each output register bit independently contro ls the operation of its res pective output pin. the function of each output pin, except for brst (pins 94 and 95), is determined by t he data stored in the output configuration register. chip select outputs output lines 0-3 (pins 84-87) are programmable as chip sele cts (cs0-cs3) via the output configuration register. when programmed as a chip select, the output pi n will go low during bus operations if its a ssociated bit in the output register is set. if the associated bit is not set in this register, the output pin will remain high. strobe outputs output lines 4-6 (pins 44-42), when progra mmed as strobes (stb0-stb2) via the outp ut configuration register, will pulse low for two busclk periods when the associated bit is set. the strobes recover and may be re-written at any time. note: the strobe output register bits are rese t automatically after the strobe is generated. auto-power output output line 6 (pin 42), when programmed as auto-power (npwr) , via the output configuration register, will remain at a high level as long as host activity is detected. when the ch ip determines that power may be shut off, this pin will go low. there are two mechanisms driving this output. the first me chanism monitors the levels on the host port. if the port assumes the terminated levels or all low levels for 16 to 20 se conds, then the host is presumed off (or disconnected). the second mechanism monitors host port activi ty (signal transitions). after a one minut e period of inactivity (given that the wdogen pin is tied low) the watchdog will be triggered sendi ng four beeps to the piezo driv er. after completion of the tones the auto-power pin will go low. general purpose outputs bit 7 (breset) and any other bits that are programmed thro ugh the output configuration register as general purpose output bits are inverted and passed to the associated output pin.
smsc ds ? PPC34C60 page 22 rev. 06/01/2001 advanced information sound register - 0011 (write only) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 freq ltone stone squlch rsvrd rsvrd rsvrd rsvrd these bits allow the piezo driver to generate tones under program control. bits 0-3:rsvrd these bits are reserved and should be written as zeros. bit 4:squlch setting this bit terminates currently active low battery tones . if the low battery input (pin 35) goes high, and then low agai n after this bit is set, low battery tones w ill resume. in order to squelch these low battery tones, this bit simply needs to be re-written with a logic "1". bit 5:stone setting this bit generates a 1/8 second tone. this bit self-clears after the tone is generated and when set again will generate another 1/8 second tone. bit 6:ltone setting this bit generates a 1/2 second tone. this bit self-clears after the tone is generated and when set again will generate another 1/2 second tone. bit 7:freq this bit selects the nominal frequency for the piezo driv er circuit. 0 selects 2khz, 1 selects 4 khz . input register - 0011 (read only) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 lobatt irq irq latch qic-80 in3 in2 in1 in0 the PPC34C60 has six input pins, of whic h two are dedicated and four are uncommitte d. the input regist er provides the host with bit access to each of these input pins. bit 4 is a special purpos e bit useful for qic-80 tape drive peripherals. bit 0:in0 (pin 82) this bit represents the current stat e of the uncommitted input pin in0. bit 1:in1 (pin 83) this bit represents the current stat e of the uncommitted input pin in1. bit 2:in2 (pin 37) this bit represents the current stat e of the uncommitted input pin in2. bit 3:in3 (pin 36) this bit represents the current stat e of the uncommitted input pin in3. bit 4:qic-80 this bit will be set if more than 2.5ms have passed since the last rising edge of ir q (pin 48). this function is designed for qic-80 tape drives that require 2.5m s between the completion of one comm and and the start of a subsequent command. bit 5:irq latch this bit is used to latch an interrupt request event and is enabled by setting inten (bit 6 of t he operation register). when enabled this bit is set by a rising edge on the irq pin (pin 48), and cleared by setting intclr (bit 7of the operation register), or by following a clear interrupt command fr om the daisy chain control packet (see the daisy chain specification - reference 3). bit 6:irq (pin 48) this bit represents the curr ent state of the irq pin. bit 7:lobatt (pin 35) this bit represents the current state of the lobatt input. w hen low, the piezo driver circuitry will provide a "low battery
smsc ds ? PPC34C60 page 23 rev. 06/01/2001 advanced information beep."
smsc ds ? PPC34C60 page 24 rev. 06/01/2001 advanced information operation register - 0100 (read/write) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 intclr inten auto-inc pdma direc dmaen d16 f16 the bits in this regi ster control the operation of the PPC34C60. bit 0:f16 setting this bit overrides pin 81 (nio16), forcing all bus acce sses to 16-bit. use this bit to access a 16-bit peripheral whic h does not generate nio16. bit 1:d16 this bit controls the bus width of the dma cycles. 1 selects 16-bit, 0 sele cts 8-bit. nio16 and f 16 are ignored during dma cycles. bit 2:dmaen this bit must be set for the dma state machine to recognize dreqs. this bit will be automatically cleared when the dma is complete. bit 3:direc this bit controls the direction of dram - bus dma cycles. 1 selects a write from dram to bus, 0 selects a read from bus to dram. bit 4:pdma setting this bit enables the psuedo-dma mode. in the pdma mode dma functions are perform ed, but cs is used instead of dack to qualify the bus cycles. use the pdma mode to dm a to or from a device which does not explicitly support dma. bit 5:autoinc setting this bit causes the bus address (a 0-a7) to increment after every bus access. bit 6:inten setting this bit enables the interrupt latch. bit 7:intclr writing a 1 to this bit will clear any pending interrupt. this bit always reads 0. dram buffer size register - 0101 (read/write) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 dma dram buffer size host dram buffer size this register determines the size of the dram buffers, both for dma dram and host dram accesses. the buffer sizes are encoded as follows: 0001 = 2 bytes 1001 = 512 bytes 0010 = 4 bytes 1010 = 1 k bytes 0011 = 8 bytes 1011 = 2 k bytes 0100 = 16 bytes 1100 = 4 k bytes 0101 = 32 bytes 1101 = 8 k bytes 0110 = 64 bytes 1110 = 16 k bytes 0111 = 128 bytes 1111 = 32 k bytes 1000 = 256 bytes 0000 = 64 k bytes
smsc ds ? PPC34C60 page 25 rev. 06/01/2001 advanced information host dram buffer pointer register - 0110 (read/write) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 host dram buffer pointer (0-255) this register sets the host's dram pointer to the sele cted buffer. the dram address is calculated using this pointer, the dram buffer size register, and the dram bus width from the conf iguration register. if maxcnt is set during the host to dram transfer, then this register is in cremented upon reaching maximum count, and the dram address is recalculated for the next buffer. a maximum of 256 buffers are available in this register. the actual number of buffe rs depends on the dram loaded, and the buffer size selected. if the pointer is incremented past the last buffer, it will wrap back around to the first buffer. no active buffer count is maintained ; the driver software must prev ent overwriting existing buffers. dma dram buffer pointer register - 0111 (read/write) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 dma dram buffer pointer (0-255) this register sets the dma dram pointer to the selected buffer. its operation is similar to the host dram buffer pointer register. this register is incremented upon co mpletion of a dma transfer and t he dram address is recalculated for the next buffer. host max block byte-count low register - 1000 (read/write) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 host max block byte-count low (hbc[7:0]) this register sets the low byte of t he counter for host block transfers. it is used in conjunction with maxcnt in the configuration register to limit external dram and bus read accesses. the c ounter is reloaded with this value at every address write cycle. host max block byte-count high register - 1001 (read/write) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 host max block byte-count high (hbc[15:8]) this register sets the high by te of the counter for host bl ock transfers. it is used in conjunction with maxcnt in the configuration register to limit external dram and bus read accesses. the c ounter is reloaded with this value at every address write cycle. dma byte-count low register - 1010 (read/write) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 dma byte-count low (dbc[7:0]) this register sets the low byte of the 16-bit byte counter used for terminati ng dma transfers. subsequent dma transfers with the same byte count can be kicked off by rese tting the dma enable bit in the operation register. dma byte-count high register - 1011 (read/write) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 dma byte-count high (dbc[15:8]) this register sets the high byte of the 16-bit byte counter used for terminat ing dma transfers. s ubsequent dma transfers with the same byte count can be kicked off by rese tting the dma enable bit in the operation register.
smsc ds ? PPC34C60 page 26 rev. 06/01/2001 advanced information configuration register - 1100 (read/write) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rst maxcnt sfifo rsvrd ra msz1 ramsz0 cksel1 cksel0 the bits in this regi ster define the configur ation of the system. bit 7:rst setting this bit resets the storage elements in the chip. bit 6:maxcnt when this bit is set, the max block count regist ers are used to limit the bus and dram accesses. bit 5:sfifo this bit selects the operating mode of the read fifo. setting th is bit causes the internal read fifo to operate as a single- word read-ahead. if this bit is clear, the read fifo will operate as a two-word read-ahead. bit 4:rsvrd this bit is reserved and should be written as zeros. bits[3:2]:ramsz[1:0] ramsz1 ramsz0 dram bus width 0 0 selects dram data width of 4 bits. 0 1 selects dram data width of 8 bits. 1 x selects dram data width of 16 bits. bits[1:0]:cksel[1:0] cksel1 cksel0 bus cycle (busclk) 0 0 bus cycle (busclk) = system clock / 2 0 1 bus cycle (busclk) = system clock / 3 1 0 bus cycle (busclk) = system clock / 5 1 1 bus cycle (busclk) = system clock / 6 busclk clocks the bus interface state machine res ponsible for generating bus access, dram access, and dram refresh timing. busclk is also responsible for output st robe timing. system clock is the sclk input (pin 96) and is typically 24mhz.
smsc ds ? PPC34C60 page 27 rev. 06/01/2001 advanced information chip revision level register - 1101 (read only) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 type id revision it is expected that the PPC34C60 will be used in various designs at different integration levels . this register provides a means of determining which type of chip is in use. the most significant five bits are reserved for a type id; the least significant three bits may be used to identify different masks and/or process types. this document refers to chips with revision level values: 0000 0000 port test write register - 1110 (write only) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 incrementing write test pattern the port test write register is used to determine the highest reliable printer port dat a transfer rate. an interface test must be performed at various speeds until data integrity can be assured. to enable this test, select t he port test write register with an address write cycle. after being selected, the register looks for an incrementing pattern starting at 00. if data i s written out of sequence, or if a communicati ons error occurs, the err bit in the data transfer control register will be set. port test read register - 1110 (read only) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 incrementing read test pattern the port test read register verifies the read data transfer rate. to enable this test , select the port test read register with an address write cycle. after being selected, this regist er reads 00 when first addressed, and increments with every access. the err bit in the data transfer control register is not a ffected by the port test read. data transfer control register - 1111 (read/write) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 err rsvrd rsvrd rsvrd rsvrd rsvrd burst 8bit bits 0 and 1 of this register provide options to regulat e data transfer on non-enhanced ports. bit 7 provides data transfer rate status information as described in the port test write register. bit 7:err this bit is set if an error occurs writing to the port test writ e register. it is cleared by se lecting the port test register with an address write cycle. bits 6-2:rsvrd these bits are reserved and should be written as zeros. bit 1:burst this bit is valid if the PPC34C60 is selected for compatibility mode. burst mode applies for reads and writes in byte mode and reads in nibble mode (see ieee std 1284 - reference 1). setting this bit maximizes data transfer by minimizing handshaking requirements. data is latched on each edge of the burst strobe as shown in figure 5. bit 0:8bit this bit is only valid with a bi-directional port in compatibilit y mode. setting this bit selects reverse transfer byte mode. clearing this bit selects reverse transfer ni bble mode (see ieee std 1284 - reference 1).
smsc ds ? PPC34C60 page 28 rev. 06/01/2001 advanced information figure 5 - burst mode hd[0 : 7 ] nhstb nhstb hd[0 : 7 ]
smsc ds ? PPC34C60 page 29 rev. 06/01/2001 advanced information 5 dram buffer operation the PPC34C60 provides support for a dram buffer with dma c apability. dram bus widths of 4, 8, or 16 bits may be used, with linear 20 bit addressing. dma to and from the dram may be either 8 or 16 bit cycles. the PPC34C60 will take care of matching the bus widths between the dma controller and the dram. if multip le dram accesses are necessary for a dma cycle, they will use fast page mode. dram refresh is automatic, and uses a cas before ras refr esh method. the dram is addressed as a number of buffers. the buffer size is programmable to 'power of 2' si zes between 2 and 64k bytes. a byte counter is used to control the dram access. it may be programmed to any value fr om 1 up to the buffer size. to prevent overwriting data, the byte counter should not be set to a value exceeding the buffer size. the dram may be independently accessed by the host and the dma controller. there are separate buffer and byte counters for each. when a dram transfer is complete, the buffer number is incremented, and further dram access is blocked. dram linear address mapping ma9 ma8 sa7 sa6 sa5 sa4 sa3 sa2 sa1 sa0 row a19 a17 a15 a14 a13 a12 a11 a10 a9 a8 col a18 a16 a7 a6 a5 a4 a3 a2 a1 a0 64k x n 256k x n 1m x n
smsc ds ? PPC34C60 page 30 rev. 06/01/2001 advanced information 5.1 dram physical addressing users access the PPC34C60 dram through the host and dma logical addressing controls found in the internal registers. the system automatically ca lculates the physical dram addresses based on t he values stored in these registers and the width of the system data paths. the logical addressing controls are the 4-bit encoded host and dm a dram buffer size controls in the dram buffer size register (0101h) and the 8-bit dram buffer pointers in t he host dram buffer pointer register (0110h) and the dma dram buffer pointer register (0111h). the dram data bus width is determined by ramsz0 and ramsz1, bits 2 and 3, in the configuration regist er (1100h). the system dma data bus width is determined by d16, bit 1 in the operation register (0100h). host acce ss is always eight bits. the PPC34C60 determines physical dram addresses by calcul ating the buffer start address and adjusting this value for bus width. the buffer start address is the buffer pointer multiplied by the buffer size . if the dram bus width is greater tha n or equal to the system bus width then the buffer start addre ss is the physical dram address, otherwise the physical dram address is the buffer start address multiplied by the system bus width divided by the dram bus width as shown in the figure 6 below. figure 6 - dram physical addressing host/dma bus width great er than dram bus width physical address = buffer ptr * buffer size * system bus width / dram bus width host/dma bus width less than or equal to dram bus width physical address = buffer ptr * buffer size for example, during a dma transfer where; 1. the dram data bus width is four bits, 2. the dma device data bus width is sixteen bits, 3. the dma buffer size is 4096 bytes (1000h), 4. the dram buffer pointer is 2, the physical dram address for the st art of this transfer will be 32768 (8000h)
smsc ds ? PPC34C60 page 31 rev. 06/01/2001 advanced information 6 system data bus cycles the system data bus is controlled by an internal state machine with seven states as shown below in figure 7. the state machine is clocked by the busclk which is software- programmable as sclk divided by 2, 3, 5, or 6. three types of operations are performed by the bus interface: a bus cycle, a dram access, and a dram refresh. refer to tables 4-6 for the state flow description for each operation. the bus controller normally sits in the idle state. when a bus interface operation is kicked off, it advances to state 1. it then advances to the next state at every busclk cycle. after state 7, the controller returns to idle. figure 7 - generic system data bus cycle bus cycle timing when an address write cycle selects a bus wr ite, the next data received is written to the bus. the interface must, however, know whether to expect an 8 or 16 bit bus address. to determi ne the bus width, a bus cycle is started from the address write cycle. this "pre-write" cycle asserts chip select and samples and latches nio16. the wr ite cycle is initiated after th e first byte received for 8 bit writes, or afte r the second byte of data for 16 bit writes. table 4 - bus cycle state flow description idle write: data bus drivers are disa bled, nras and ncas are inactive. state 1 read: if necessary, data advances to next element in the fifo buffer. ncas goes active fo r first refresh. state 2 write: data is latc hed into bus latches. nras goes active fo r first refresh. state 3 chip select goes active. state 4 nio16 is sampled. read: nrd goes active. write: if nio16 is sampled low and this is the first byte received, then nwr remains inactive. if nio16 is sampled high or if nio16 is sampled low and this is the second byte received, then nwr goes active and data bus drivers are enabled. nras and ncas go inactive. state 5 wait for data bus to stabilize, nc as goes active for second refresh. state 6 read: data is latched, nrd goes inactive. write: nwr goes inactive. nras goes active for second refresh. state 7 chip select goes inactive. read: data advances to next element if possible. write: data bus drivers are disabled. table 5 - dram access state flow description idle nras and ncas go inactive. state 1 row address output. state 2 nras goes active. read: nrd goes active. write: nwr goes active. state 3 column address output write: data bus drivers enabled. state 4 ncas goes active. state 5 column address incremented. read: data is latched. write: data bus drivers disabled. (if multiple accesses are neede d, states 3-5 are repeated) state 6 nras, ncas, nrd, nwr go inactive. state 7 nras precharge time. idle state 1 state 2 state 3 state 4 state 5 state 6 st at e 7
smsc ds ? PPC34C60 page 32 rev. 06/01/2001 advanced information table 6 - dram refresh state flow description * idle nras and ncas go inactive. state 1 ncas goes active fo r first refresh. state 2 nras goes active fo r first refresh. state 3 state 4 nras and ncas go inactive. state 5 ncas goes active for second refresh. state 6 nras goes active for second refresh. state 7 *for sclk = 24 mhz, a dram refresh cycle is performed every 30 s. bus cycles have built-in dram refresh which reset the 30 s refresh timer. powering the PPC34C60 the PPC34C60 has a built-in mechanism to insure against da mage when the peripheral is po wered down and the host is powered up. figure 8 shows how to incorporate this protection feature in to your peripheral's power and return design. isolate the chip's vcc from the rest of the peripheral's vcc using a schottky diode. the sense input should be tied to the peripheral's vcc and the anode of the diode. w hen the peripheral's power is off, the sen se input will go low, tri-stating all outputs. this prevents the pp c34c60 from driving into a low impedance l oad and damaging its input protection diodes. when the peripheral's power is turned on, the sense line will be pulled high and all output drivers of the PPC34C60 will be enabled. figure 8 - suggested pp PPC34C60 .01uf .01uf .01uf .01uf .01uf .01uf schottky diode, vrb > 10v 1n5818 - under 1 amp 1n5821 - 1-3 amps power supply vcc sense 33 9 21 41 60 72 90 91 71 59 40 22 10 vcc gnd to v c c fo r th e rest of the system.
smsc ds ? PPC34C60 page 33 rev. 06/01/2001 advanced information suggested oscillator circuits the PPC34C60 requires two frequency sources. the 24mhz cloc k is supplied with a parallel resonant 24mhz crystal oscillator connected as shown in figure 9. it is important that the board designer place the crystal oscillator close to the PPC34C60 maintaining the shortest possible traces. the 24mhz clock is used by much of the internal circuitry and provides the time base used by the bus interface circuitry. the second clock source is provided by an rc circuit and s hould be connected as shown in figure 10. this clock is used primarily by the watch dog timer and piezo driver functional blocks. PPC34C60 xin xout 24mhz crystal 20 pf 20 pf figure 9 - suggested 24 mhz oscillator circuit figure 10 - suggested 32 khz oscillator circuit PPC34C60 yin yout r 2.2 k 100 .068 uf
smsc ds ? PPC34C60 rev. 06/01/2001 advanced information 7 operational description maximum guaranteed ratings* operating tem perature range.................................................................................................... ............................0 o c to +70 o c storage temper ature range ...................................................................................................... .......................... -55 o to +150 o c lead temperature range (sol dering, 10 seconds )................................................................................. ......................... +325 o c positive voltage on any pin, with respec t to ground............................................................................ .......................vcc+0.3v negative voltage on any pin, with respec t to ground ............................................................................ ............................. -0.3v maximum vcc.................................................................................................................... ....................................................+7v *stresses above those listed above coul d cause permanent damage to the device. this is a stress rating only and functional operation of the device at any other condition above those indicated in the operation sect ions of this specification is not implied. note: when powering this device from labor atory or system power supplies, it is important that the absolute maximum ratings not be exceeded or device failure can result. some power supplies exhibit voltage sp ikes on their outputs when the ac power is switched on or off. in addition, voltage transie nts on the ac power line may appear on the dc output. if this possibility exists, it is suggested that a clamp circuit be used. dc electrical characteristics (ta = 0 o c - 70 o c, vcc = +5.0 v 10%) parameter symbol min typ max units comments i type input buffer low input level high input level schmitt trigger hysteresis v ilis v ihis v hys 2.2 250 0.8 v v mv schmitt trigger schmitt trigger iclk input buffer low input level high input level v ilck v ihck 3.0 0.4 v v input leakage (all i and is buffers) low input leakage high input leakage i il i ih -10 -10 +10 +10 a a v in = 0 v in = v cc pull up current i oh 75 150 a v in = 0 pull down current i ol 200 a v in = 5 parameter symbol min typ max units comments i/o8 type buffer low output level high output level output leakage v ol v oh i ol 2.4 -10 0.4 +10 v v a i ol = 8 ma i oh = -4 ma v in = 0 to v cc i/o16 type buffer low output level high output level v ol v oh 2.4 0.4 v v i ol = 16 ma i oh = -12 ma
smsc ds ? PPC34C60 page 35 rev. 06/01/2001 advanced information parameter symbol min typ max units comments output leakage i ol -10 +10 a v in = 0 to v cc o8 type buffer low output level high output level output leakage v ol v oh i ol 2.4 -10 0.4 +10 v v a i ol = 8 ma i oh = -4 ma v in = 0 to v cc o16 type buffer low output level high output level output leakage v ol v oh i ol 2.4 -10 0.4 +10 v v a i ol = 16 ma i oh = -12 ma v in = 0 to v cc o24 type buffer low output level high output level output leakage v ol v oh i ol 2.4 -10 0.4 +10 v v a i ol = 24 ma i oh = -12 ma v in = 0 to v cc supply current active i cc 80 ma all outputs open. capacitance t a = 25 o c; fc = 1mhz; v cc = 5v limits parameter symbol min typ max unit test condition clock input capacitance c in 20 pf all pins except pin under test tied to ac ground input capacitance c in 10 pf output capacitance c out 20 pf
smsc ds ? PPC34C60 rev. 06/01/2001 advanced information 8 timing diagrams the PPC34C60 supports three communications cycles: address writ e, data write, and data read. the signaling for these cycles in standard, epp, and ecp modes is discussed below. address write an address write cycle must be issued before any data cycl es, since this tells the PPC34C60 whether the following data cycles are write/read, and where the data should go/come from. standard mode the host places the address information on the parallel port dat a lines, then strobes the address into the PPC34C60 by pulsing select in (hsel) low with a minimum 200 ns pulse wi dth. the PPC34C60 will always accept the address write cycle, there is no busy hold off. epp mode the host sends address information by writing to the epp address register (base+3). the epp interface chip places this data on the parallel port data lines, then br ings select in (hsel) low. the PPC34C60 latches the information, then acknowledges the transfer by raising busy (hbsy). the epp in terface chip may terminate the cycle when it sees busy go high. ecp mode the host sends address information by writing to the ecp addre ss fifo (base+0). the ecp inte rface chip places this data on the parallel port data lines, sets auto lf (half) low to i ndicate address information, then sets strobe (hstb) low to start the transfer. the PPC34C60 acknowledges the cycle by rais ing busy (hbsy). the ecp chip then raises strobe. the PPC34C60 latches the information, then sets busy low. data write the data write cycle is used to send data to the PPC34C60 regist ers, dram, or the remote system. a previous address write cycle must have been sent to the PPC34C60 sele cting write, and the target of the write. standard mode if the PPC34C60 can accept data, busy (hbsy) will be low. t he host places the data on the parallel port data lines, then strobes the data into the PPC34C60 by pul sing strobe (hstb) low with a minimum 200 ns pulse width. if the PPC34C60 is operating in the burst mode, then strobe s hould only change state instead of pulsing low. epp mode if the PPC34C60 can accept data, busy (hbsy) will be low. the host sends data by writing to the epp data registers (base+4 - base+7). the epp interface chip places the data on the parallel port data lines, then lowers auto lf (half). the PPC34C60 latches the data, then raises busy to acknowl edge the transfer. the epp inte rface chip may terminate the cycle when it sees busy go high. ecp mode if the PPC34C60 can accept data, busy (hbsy) will be low. the host sends data by writ ing to the ecp data fifo (base+400h). the ecp interface chip places this data on the par allel port data lines, sets auto lf (half) high to indicate data cycle, then lowers strobe (hstb) to start the transfer. the PPC34C60 acknowledges the cycle by raising busy. the ecp chip then raises strobe. the PPC34C60 latches the data, then sets busy low. data read a data read cycle is used to get data from the PPC34C60 regist ers, dram, or the remote sy stem. a previous address write cycle must have been sent to the PPC34C60 selecting read, and the source of the read. standard mode if the PPC34C60 has data ready, busy (hbsy) will be low. if the PPC34C60 is in 4 bit mode, the host reads the low nibble from the status lines ack (hack), perror (hpe), slct (hslct), error (herr). the host then pulses strobe (hstb) low to acknowledge the low nibble. the PPC34C60 then places the high nibble on the same status lines, the host reads the high nibble, then pulses strobe to signal receipt of the data. if the PPC34C60 is in 8 bit mode, t hen the host disables it's data drivers, floating the parallel port data lines. the host enables the PPC34C60 bus dr ivers by lowering init (hinit), reads the data from the data lines, then pulses strobe low to acknowle dge the transfer. if the ppc34c 60 is operating in burst mode, then the strobe only changes st ate instead of pulsing low in the above description. epp mode if the PPC34C60 has data ready, busy (hbsy) will be low. the host gets data from the PPC34C60 by reading the epp data registers (base+4-base+7). the epp interface chip disabl es the port drivers, then lowers auto lf (half). at this point, the PPC34C60 drives data onto the data lines, then rais es busy. the epp chip then latches the data, and raises auto lf to terminate the cycle.
smsc ds ? PPC34C60 page 37 rev. 06/01/2001 advanced information ecp mode the ecp interface requests a reverse transfer by disabling the data line drivers, then lowering inet (hinit). the PPC34C60 acknowledges the reverse transfer by lowering pe rror (hpe), and driving the data lines. when the PPC34C60 has data ready, it will lower ack (hack). the ecp chip w ill respond by raising auto lf (half). the PPC34C60 then raises ack, signaling the ecp chip to latch the data. the ecp chip then terminates the cycle by lowering auto lf. timing symbol PPC34C60 pin name pin number hd[0:7] hd[0:7] 5,8,13,15-18,20 nstb nhstb 2 nalf nhalf 3 nsel nhsel 14 ninit nhinit 11 bsy hbsy 26 nack nhack 24 pe hpe 28 slct hslct 30 nerr nherr 6 figure 11 - spp address write timing (parallel port signals) all timing for sclk = 24mhz. this signaling sequence pertains to a device that has been previous ly selected to communicate via spp mode. this timing sequence is not specified in t he p1284 specification; it shoul d not violate the p1284 spec. see spp address write timing parameters. t1 t5 t6 t2 t4 t3 hd[0:7] nstb h nalf h nsel h ninit h bsy p nack p pe p slct p nerr p
smsc ds ? PPC34C60 page 38 rev. 06/01/2001 advanced information spp address write timing (parallel port signals) parameter min typ max units t1 ninit controls the direction of the parallel port when in spp mode. ninit deasserted to hd[0:7] released to high impedance by the PPC34C60. 84 [2 sclk] 125 [3 sclk] ns t2 the host can now drive hd[0:7] with an address byte and then strobe it into the PPC34C60 by asserting the nsel signal. this time represents the address setup time required by the PPC34C60. 125 [3 sclk] ns t3 typically the address written to the PPC34C60 is an instruction detailing the type of transfer to follow (i.e., data read/write to dram, bus, register). thus, once this address is received by the PPC34C60, it asserts the bsy signal to indicate that it is preparing for the upcoming transfer. this time represents the time for bsy to assert from the assertion of nsel. 167 [4 sclk] 208 [5 sclk] ns t4 nsel pulse width. this time represents the duration that nsel must be asserted in order for the PPC34C60 to recognize an edge. 125 [3 sclk] ns t5 the host is required to hold the address valid for this amount of time following assertion of the nsel line. 167 [4 sclk] ns t6 ninit controls the direction of the parallel port when in spp mode. ninit may be asserted anytime after the address hold time (t5) has been satisfied. this time represents the time from ninit asserted to hd[0:7] driven by the PPC34C60. 84 [2 sclk] 125 [3 sclk] ns
smsc ds ? PPC34C60 page 39 rev. 06/01/2001 advanced information figure 12 - spp data write timing (parallel port signals ) this signaling sequence pertains to a dev ice that has been previously selected to communicate via spp mode. spp data write timing (parallel port signals) parameter min typ max units t1 ninit controls the direction of the parallel port when in spp mode. ninit deasserted to hd[0:7] released to high impedance by the PPC34C60. 84 [2 sclk] 125 [3 sclk] ns t2 valid data on hd[0:7] to nstb asserted edge. 125 [3 sclk] ns t3 bsy deasserted (low) to nstb asserted edge. 0 ns t4 nstb asserted pulse width. 125 [3 sclk] ns t5 valid data hold from nstb deasserted edge. 125 [3 sclk] ns t6 nstb asserted edge to bsy asserted edge. 333 [8 sclk] 375 [9 sclk] ns t7 bsy asserted pulse width. these values are based on bclk = 2 sclk. 0 1,084 [13 bclk] ns t1 t5 t5 t2 t3 t4 t2 t3 t4 t6 t7 t6 hd[0:7] nstb h nalf h nsel h ninit h bsy p nack p pe p slct p nerr p
smsc ds ? PPC34C60 page 40 rev. 06/01/2001 advanced information figure 13 - spp data read timing (parallel port signals) this signaling sequence pertains to a devic e that has been previously selected to communicate via spp mode. the timing sequence shows three bytes being read from the 34c60. see spp data read timing parameters. t1 t6 t7 t6 t7 t8 t3 t4 t3 t4 t2 t5 t2 t5 t2 hd[0:7] nstb h nalf h nsel h ninit h bsy p nack p pe p slct p nerr p
smsc ds ? PPC34C60 page 41 rev. 06/01/2001 advanced information spp data read timing parameter min typ max units t1 ninit controls the direction of the parallel port when in spp mode. when ninit is asse rted the data port is driven by the PPC34C60 and read by the host. this time represents the time from ninit asserted to hd[0:7] driven by the PPC34C60. note: data is not necessarily valid. 84 [2 sclk] 125 [3 sclk] ns t2 as soon as the PPC34C60 pl aces valid data onto the hd[0:7] port lines, the bsy signal is deasserted by the PPC34C60 to inform the host that data is now valid. 0 20 ns t3 this time is determined by the host, the PPC34C60 places no restriction on this time. this time represents the time it takes the host to recognize and latch the valid data on hd[0:7]. n/a n/a t4 nstb pulse width. this time represents the duration that nsel must be asserted in order for the PPC34C60 to recognize an edge. 125 [3 sclk] ns t5 once the host has latched the data on hd[0:7] it asserts the nstb signal to inform the PPC34C60 to fetch another byte of data. if the ppc34c 60 has to perform a dram or bus cycle it may have to assert the bsy signal until it has completed the cycle and has placed valid data on hd[0:7]. this time represents the time from the assertion of nstb to the assertion of bsy when appropriate. 334 [8 sclk] 375 [9 sclk] ns t6 once the host has latched the data on hd[0:7] it asserts the nstb signal to inform the PPC34C60 to fetch another byte of data. this time represents the time that the hd[0:7] data will remain valid from the assertion of nstb. 84 [2 sclk] 125 [3 sclk] ns t7 this time (+t6) represents the time it takes the PPC34C60 to fetch and present the next va lid data byte on the hd[0:7] lines. this time will vary significantly based on the type of access and the bclk currently selected. these values are based on bclk = 2 sclk. 250 [6 sclk] 1,292 [5 sclk] + [13 bclk] ns t8 ninit controls the direction of the parallel port when in spp mode. ninit deasserted to hd[0:7] released to high impedance by the PPC34C60. 84 [2 sclk] 125 [3 sclk] ns
smsc ds ? PPC34C60 page 42 rev. 06/01/2001 advanced information figure 14 - spp nibble read (parallel port signals) this signaling sequence pertains to a device that has been previous ly selected to communicate via spp mode. this timing sequence deviates from that specified in the p1284 specification. it is implem ented in a way that requires less host software overhead and therefor e affords higher bandwidth. the timing shown is for a nibble read of a 16 bit wide res ource (dram or peripheral bus). see spp nibble read timing parameters. t2 t4 t5 t6 t4 t5 t6 t4 t5 t6 t4 t1 t7 t8 t3 t3 t3 t3 bit d3 bit d7 bit d2 bit d6 bit d1 bit d5 bit d0 bit d4 bit d8 bit d9 bit d10 bit d11 bit d12 bit d13 bit d14 bit d15 nstb h nalf h nsel h ninit h bsy p nack p pe p sclt p nerr p
smsc ds ? PPC34C60 page 43 rev. 06/01/2001 advanced information spp nibble read (parallel port signals) parameter min typ max units t1 the PPC34C60 assembles a nibble of data and places it on the status lines. the PPC34C60 then deasserts the bsy signal to inform the host that a valid nibble is available. 42 [sclk] ns t2 once the host senses that the bsy line is deasserted it will then internally latch the nibble and then assert nstb to tell the PPC34C60 to get the next nibble. 0 ns t3 it will take the PPC34C60 this amount of time to fetch and present the next nibble of data. 250 [6 sclk] ns t4 nstb asserted pulse width 125 [3 sclk] ns t5 nstb deasserted pulse width 125 [3 sclk] ns t6 once the PPC34C60 has placed t he next nibble, this is the time for the host to latch the nibble and then assert nstb to tell the PPC34C60 to get the next nibble. 42 [sclk] ns t7 once the host has latched the last nibble it asserts the nstb signal to inform the PPC34C60 to fetch another more data. if the PPC34C60 has to perform a dram or bus cycle it may have to assert the bsy signal until it has completed the cycle and has placed a valid nibble on the status lines. this time represents the time from the assertion of nstb to the assertion of bsy when appropriate. 334 [8 sclk] 375 [9 sclk] ns t8 this time represents the time it takes the PPC34C60 to fetch and present the next valid nibble on the status lines. this time will vary significantly based on the type of access and the bclk currently select ed. these values are based on bclk = 2 sclk. 0 1,084 [13 bclk] ns
smsc ds ? PPC34C60 page 44 rev. 06/01/2001 advanced information figure 15 - epp address write (parallel port signals) epp timing is ieee p1284 compat ible except the PPC34C60: 1) does not use ninit to terminate epp mode (return to compatibility mode) 2) does not support using nack to generat e interrupts to the host while selected. see epp address write timing parameters. epp address write (parallel port signals) parameter min typ max units t1 the host asserts nstb. at the same time the host places the address byte on hd[0:7]. this specifies the jitter between nstb being asserted and an address appearing on hd[0:7]. the PPC34C60 does not rely on nstb. 0 50 ns t2 the nslctin signal is asserted coincident with the above events to indicate that an epp address cycle is to take place. this time represents the jitter margin between nslctin asserted and the above two events. 0 50 ns t3 the PPC34C60 will detect the assertion of nslctin and will assert bsy to indicate that it has latched the address on hd[0:7]. 250 [6 sclk] 10,000 ns t4 after the PPC34C60 asserts bsy the host will then indicate that the cycle is complete by deasserting nslctin. this represents the response time requirements put on the host. 42 [sclk] ns t5 seeing that the host has in dicated that the cycle is complete, the PPC34C60 will then deassert the bsy line as soon as it is ready for another epp transfer. 209 [5 sclk] ns t6 as soon as the PPC34C60 deasserts bsy the host may initiate another epp transfer. this time represents the time between the PPC34C60 deasserting bsy to the host starting a new transfer cycle. 0 ns t1 t1 7 t2 t4 t3 t5 valid address hd[0:7] nstb h nalf h nslctin h ninit h bsy p nack p pe p slcl p nerr p
smsc ds ? PPC34C60 page 45 rev. 06/01/2001 advanced information figure 16 - epp data write timing (parallel port signals) see epp data write timing parameters. epp data write timing (parallel port signals) parameter min typ max units t1 the host asserts nstb to indicate that the forthcoming transfer is a write cycle. at the same time or soon after the host places the address byte on hd[0:7]. this specifies the time between nstb being asserted and an address appearing on hd[0:7]. the PPC34C60 does not rely on nstb. 0 ns t2 after placing an address on hd[0:7], the host then asserts nalf to inform the PPC34C60 that a data cycle is taking place. 0 ns t3 the PPC34C60 will detect the assertion of nalf and will assert bsy to indicate that it has latched the data on hd[0:7]. 250 [6 sclk] 10,000 ns t4 after the PPC34C60 asserts bsy the host will then indicate that the cycle is complete by deasserting nalf. this represents the response time requirements put on the host. 42 [sclk] t5 seeing that the host has indicated that the cycle is complete, the PPC34C60 will then deassert the bsy line as soon as it is ready for another epp transfer. 209 [5 sclk] ns t6 as soon as the PPC34C60 deasserts bsy the host may initiate another epp transfer. this time represents the time between the PPC34C60 deasserting bsy to the host starting a new transfer cycle. 0 ns t1 t1 t6 t2 t4 t3 t5 valid data hd[0:7] nstb h nalf h nsel h ninit h bsy p nack p pe p slct p nerr p
smsc ds ? PPC34C60 page 46 rev. 06/01/2001 advanced information figure 17 - epp data read timing (parallel port signals) see epp data read timing parameters. epp data read timing (parallel port signals) parameter min typ max units t1 the host deasserts nstb to indicate that the forthcoming transfer is a read cycle. at the same time or soon after the host will release the parallel por t data lines hd[0:7] to a high impedance state. this specifies the time between nstb being asserted and an address appearing on hd[0:7].the PPC34C60 does not rely on nstb. 0 t2 after tri-stating the hd[0:7] lines, the host then asserts nalf to inform the PPC34C60 that a data cycle is taking place. 0 t3 the PPC34C60 will respond by placing data on hd[0:7]. 125 [3 sclk] 1,084 [13 bclk] ns t4 then the PPC34C60 will assert the bsy line to inform the host that it has placed a valid byte of data on the parallel port data lines hd[0:7]. 125 [3 sclk] 167 [4 sclk] ns t5 next, the host latches the data on hd[0:7] and deasserts nalf to inform the PPC34C60 that the cycle is complete. 42 [sclk] ns t6 in response, the PPC34C60 tri-states the parallel port data lines hd[0:7]. 209 [5 sclk] ns t7 after tri-stating hd[0:7] the PPC34C60 deassert bsy to indicate that it is now ready for the next epp transfer. 42 [sclk] ns t8 as soon as the PPC34C60 deasserts bsy the host may initiate another epp transfer. this time represents the time between the PPC34C60 deasserting bsy to the host starting a new transfer cycle. 0 ns t1 t3 t6 t1 t8 t2 t5 t4 t7 valid data hd[0:7] nstb h nalf h nsel h ninit h bsy p nack p pe p slct p nerr p
smsc ds ? PPC34C60 page 47 rev. 06/01/2001 advanced information figure 18 - ecp forward command transfer timing (ecp address write, parallel port signals) see ecp forward command transfer timing parameters. ecp forward command transfer timing (ecp address write, parallel port signals) parameter min typ max units t1 the host places data on hd[0:7] and at the same time asserts nalf to indicate that this is a command transfer. (the PPC34C60 supports address commands, not rle commands) 0 ns t2 after placing data on hd[0:7] and asserting nalf, the host is required to meet this setup time before asserting nstb. assetion of nstb informs the PPC34C60 that valid data is on hd[ 0:7] and that nalf is valid. 0 ns t3 the peripheral acknowledges by asserting bsy. 334 [8 sclk] ns t4 once the peripheral has sent its acknowledgement the host deasserts nstb to continue the handshake. the PPC34C60 latches the address data on this rising edge of nstb. 42 [sclk] ns t5 as soon as the PPC34C60 has accepted the data and is ready to accept another byte it deasserts the bsy signal. 334 [8 sclk] ns t6 once the PPC34C60 has indicated it is ready to receive another byte of data from the host, the host if and when ready will place another byte on hd[0:7]. this time is the time required between the deassertion of bsy and new valid data on hd[0:7]. 42 [sclk] ns t6 t2 t4 t2 t1 t1 t3 t5 valid address hd[0:7] nstb h nalf h nsel h ninit h bsy p nack p pe p slct p nerr p
smsc ds ? PPC34C60 page 48 rev. 06/01/2001 advanced information figure 19 - ecp forward data transfer timing (ecp data write, parallel port signals) see ecp forward data transfer timing parameters ecp forward data transfer timing (ecp data write, parallel port signals) parameter min typ max units t1 the PPC34C60 indicates it is ready to receive another byte of data from the host by deasserting bsy. the host if and when ready will place a byte on hd[0:7]. this time is the time required between the deassertion of bsy and data on hd[0:7]. 42 [sclk] ns t2 the host places data on hd[0:7] and at the same time deasserts nalf to indicate that this is a data transfer. 0 ns t3 after placing data on hd[0:7] and deasserting nalf, the host is required to meet this setup time before asserting nstb. assetion of nstb informs the PPC34C60 that valid data is on hd[0:7] and that nalf is valid. 0 ns t4 the peripheral acknowledges by asserting bsy. 334 [8 sclk] ns t5 once the peripheral has sent its acknowledgement the host deasserts nstb to continue the handshake. the PPC34C60 latches the data on this rising edge of nstb. 42 [sclk] ns t6 as soon as the PPC34C60 has accepted the data and is ready to accept another byte it deasserts the bsy signal. 334 [8 sclk] ns t1 t1 t3 t5 t2 t2 t4 t6 valid data hd[0:7] nstb h nalf h nsel h ninit h bsy p nack p pe p slct p nerr p
smsc ds ? PPC34C60 page 49 rev. 06/01/2001 advanced information figure 20 - ecp reverse data transfer timing (ecp data read, parallel port signals) note: the optional use of the nerr (nfault) line to "hint" to t he host that the peripheral has data to send to the host is not supported in the PPC34C60. the driv er should ignore any activity on this line. the PPC34C60 supports reverse data transfers only (not reverse command trans fers) and, therefore, always asserts the bsy (ncmd) signal during reverse transfers. see ecp reverse data transfer timing parameters. ecp reverse data transfer timing (ecp data read, parallel port signals) parameter min typ max units t1 to prepare for an ecp reverse channel transfer the host tri- states the parallel data lines hd [0:7] and asserts nalf at the same time. next the host asserts ninit to initiate an ecp bus reversal. the PPC34C60 requires this amout of time between these events. 0 ns t2 the PPC34C60 acknowledges the bus reversal by deasserting the pe signal. at this point in time the parallel port bus is in the reverse idle state. 208 [5 sclk] 334 [8 sclk] ns t3 along with deasserting the pe signal the PPC34C60 takes control of the parallel port dat a bus hd[0:7]. the data on this bus remains undefined until the PPC34C60 has accessed and placed a data byte on the bus. al ong with driving the data lines with valid data, the PPC34C60 asserts bsy to indicate that this is a data transfer. 0 1,084 [13 bclk] ns t4 after placing data on the par allel port data lines the PPC34C60 asserts nack to inform the host that valid data is available. 125 [3 sclk] 167 [4 sclk] ns t5 next, the host will acknowledge t hat it is ready for the data by deasserting nalf. 50 infinite ns t6 now the PPC34C60 will deassert nack in response to the host. the host will latch the data on hd[0:7] on this rising edge of nack. 125 [3 sclk] 167 [4 sclk] ns t7 the host completes the ecp reverse transfer, acknowledging that it has accepted the data byte by asserting nalf. 50ns 1s valid data t3 t8 t9 t11 t5 t7 t1 t4 t6 t2 t10 hd[0:7] nstb h nalf h nsel h ninit h bsy p nack p pe p slct p nerr p data
smsc ds ? PPC34C60 page 50 rev. 06/01/2001 advanced information parameter min typ max units t8 at the completion of the ec p reverse transfer cycle the PPC34C60 either places another valid data byte on the data lines or if it has no more data to send goes into the idle state driving undefined data ont o the parallel port bus lines. as long as the port is in the reverse transfer mode, the PPC34C60 will always return data when a byte is requested. once host max block byte-count has been reached, the PPC34C60 will present "pad" bytes to the host. the host will discard any extra bytes received. the extra "pad" bytes are useful to provide alignment to wider buses. 125 [3 sclk] 167 [4 sclk] ns t9 the host requests that the parallel port be placed back into the forward direction by deassert ing ninit, and in response to this the PPC34C60 will terminate any ongoing data transfer and place the data bus hd[0:7] in a high impedance state and deassert the bsy line. 125 [3 sclk] 167 [4 sclk] ns t10 after releasing the bus, the pp c34c60 acknowledges that it has relinquished the bus by asserting the pe signal. 0 125 [3 sclk] ns t11 after the PPC34C60 has indicated that it has relinquished the bus, the host may drive the data bus. 0 500 ns
smsc ds ? PPC34C60 page 51 rev. 06/01/2001 advanced information figure 21 - peripheral bus read cycle timing parameter min typ max units t1 ncs asserted to nwr asserted. this applies to any and all of the general purpose out put pins that have been configured to operate as "spe cial function" chip select pins. this feature saves the designer from having to implement costly address decoders. 74 [1 bclk -10] 84 [1 bclk] 94 [1bclk +10] ns t2 nio16 setup required to the assertion of nrd. 15 ns t3 nio16 hold time required from the assertion of nrd. 10 ns t4 nrd asserted pulse width. 158 [2 bclk - 10] 168 [2 bclk] 178 [2 bclk +10] ns t5 data valid setup time required to deassertion of nrd. 15 ns t6 data valid hold time required from deassertion of nrd. 10 ns t7 nrd deasserted to ncs deasserted. 74 [1 bclk -10] 84 [1 bclk] 94 [1bclk +10] ns t8 nrd deasserted to the address incremented (this is valid only if the autoinc bit is set). 74 [1 bclk -10] 84 [1 bclk] 94 [1bclk +10] ns t7 t3 t1 t2 t4 t5 t6 t8 valid data valid address valid address+1 autoinc bit set ncas nras ncs nio16 nrd nwr sd[0:15] sa[0:7] busclk
smsc ds ? PPC34C60 page 52 rev. 06/01/2001 advanced information figure 22 - peripheral bus write cycle timing parameter min typ max units t1 ncs asserted to nwr asserted. this applies to any and all of the general purpos e output pins that have been configured to operate as "special function" chip select pins. this featur e saves the designer from having to implement costly address decoders. 74 [1 bclk-10] 84 [1 bclk] 94 [1bclk+10] ns t2 nio16 setup required to the assertion of nwr. 15 ns t3 nio16 hold time required from the assertion of nwr. 10 ns t4 nwr asserted pulse width. 158 [2 bclk-10] 168 [2 bclk] 178 [2bclk+10] ns t5 write data valid from the assertion of ncs. 74 [1 bclk-10] 84 [1 bclk] 94 [1bclk+10] ns t6 write data valid hold time from the deassertion of nwr. 74 [1 bclk-10] 84 [1 bclk] 94 [1bclk+10] ns t7 nwr deasserted to ncs deasserted. 74 [1 bclk-10] 84 [1 bclk] 94 [1bclk+10] ns t8 nwr deasserted to the addr ess incremented (this is valid only if the autoinc bit is set). 74 [1 bclk-10] 84 [1 bclk] 94 [1bclk+10] ns t7 t3 t1 t2 t4 t5 t6 t8 valid data valid address valid address +1 autoinc bit set ncas nras ncs nio16 nrd nw r sd[0:15] sa[0:7] busclk
smsc ds ? PPC34C60 page 53 rev. 06/01/2001 advanced information figure 23 - dram read cycle timing when the dram bus width (4, 8 or 16 bits) is narrower than the ho st bus (always 8-bits) or the peripheral bus (8 or 16 bits) than the PPC34C60 will implement fast page mode dram cycl es to complete the data transfer. these page mode transfers are performed for dma as well as host dram access. see dram read cycle timing parameters. dram read cycle timing parameter min typ max units t1 10-bit dram row address valid to nrd asserted. 74 [1 bclk -10] 84 [1 bclk] 94 [1bclk +10] ns t2 10-bit dram row address valid to nras asserted. 74 [1 bclk -10] 84 [1 bclk] 94 [1bclk +10] ns t3 nras asserted to valid 10-bit dram column address. 74 [1 bclk -10] 84 [1 bclk] 94 [1bclk +10] ns t4 10-bit dram column address valid to ncas asserted. 74 [1 bclk -10] 84 [1 bclk] 94 [1bclk +10] ns t5 10-bit dram column address incremented and at the same time the data is latched into the PPC34C60 following ncas asserted. 74 [1 bclk -10] 84 [1 bclk] 94 [1bclk +10] ns t6 ncas deasserted after the column address has been updated and the data has been latched by the PPC34C60. 74 [1 bclk -10] 84 [1 bclk] 94 [1bclk +10] ns t7 ncas deasserted pulse width during page mode accesses. 74 [1 bclk -10] 84 [1 bclk] 94 [1bclk +10] ns t8 ncas asserted to valid data, i.e., maximum acceptable dram access time. 0 74 [1bclk -10] ns t9 ncas deasserted to dram releasing data from the bus. 0 74 [1bclk -10] ns t10 ncas and nras both deasserted to nrd deasserted. 0 42 [1 sclk] ns t3 t5 t5 t4 t6 t7 t6 t2 t1 t10 t8 t9 t8 t9 data valid row addr row addr col addr col addr +2 col addr +1 sab data valid col addr bits 8 & 9 sab ma[8:9] sa[0:7] ncas nras nrd nwr sd[0:15] busclk
smsc ds ? PPC34C60 page 54 rev. 06/01/2001 advanced information figure 24 - dram write cycle timing when the dram bus width (4, 8 or 16 bits) is narrower than the ho st bus (always 8-bits) or the peripheral bus (8 or 16 bits) than the PPC34C60 will implement fast page mode dram cycl es to complete the data transfer. these page mode transfers are performed for dma as well as host dram access. see dram write cycle timing parameters. dram write cycle timing parameter min typ max units t1 10-bit dram row address valid to nwr asserted. 74 [1 bclk -10] 84 [1 bclk] 94 [1bclk +10] ns t2 10-bit dram row address valid to nras asserted. 74 [1 bclk -10] 84 [1 bclk] 94 [1bclk +10] ns t3 nras asserted to valid 10-bit dram column address. 74 [1 bclk -10] 84 [1 bclk] 94 [1bclk +10] ns t4 10-bit dram column address valid to ncas asserted. 74 [1 bclk -10] 84 [1 bclk] 94 [1bclk +10] ns t5 10-bit dram column address incremented following ncas asserted. 74 [1 bclk -10] 84 [1 bclk] 94 [1bclk +10] ns t6 valid write data in relation to the 10-bit column address presented by the PPC34C60. 0 10 ns t7 dram column address incremented to ncas deasserted. 74 [1 bclk -10] 84 [1 bclk] 94 [1bclk +10] ns t8 valid write data in relation to the 10-bit column address presented by the PPC34C60. 0 10 ns t9 ncas deasserted to valid data placed on the data bus. 0 10 ns t10 ncas and nras both deasserted to nwr deasserted. 0 42 [1 sclk] ns t3 t5 t4 t7 t2 t1 t10 t6 t8 t9 t8 data valid row addr row addr col addr col addr +2 col addr +1 sab data valid col addr bits 8 & 9 sab ma[8:9] sa[0:7] ncas nras nrd nwr sd[0:15] busclk
smsc ds ? PPC34C60 page 55 rev. 06/01/2001 advanced information figure 25 - dram write refresh cycle parameter min typ max units t1 ncas asserted to nras asserted. 74 [1 bclk -10] 84 [1 bclk] 94 [1bclk +10] ns t2 ncas asserted pulse width 242 [3 bclk -10] 252 [3 bclk] 262 [3 bclk +10] ns t3 nras asserted pulse width 158 [2 bclk -10] 168 [2 bclk] 178 [2 bclk +10] ns t4 ncas deasserted pulse width 74 [1 bclk -10] 84 [1 bclk] 94 [1 bclk +10] ns t5 nras deasserted pulse width 158 [2 bclk -10] 168 [2 bclk] 178 [2 bclk +10] ns t2 t4 t2 t1 t3 t1 t5 t3 ma[8:9] sa[0:7] ncas nras hd[0:7] busclk
smsc ds ? PPC34C60 page 56 rev. 06/01/2001 advanced information figure 26 - dma transfer cycle timing [8-bit peripheral system bus to 4-bi t dram], (d16=0, ramsz[1:0]=[0,0]) [16-bit peripheral system bus to 8-bi t dram], (d16=1, ramsz[1:0]=[0,1]) figure 27 - dma transfer cycle timing [8-bit peripheral system bus to 16-bit dram], (d16=0, ra msz[1:0]=[1,x]). dma tern=m inal count goes high coincident with ndack for last transfer. see page 72 for dma transfer cycle timing parameters. row addr col addr row addr col addr col addr +1 col addr +2 col addr +3 system bus address data data data ma[9:8] sa[7:0] nras ncas dreq ndack sdbus nrd nwr col addr system bus address data data data row addr row addr col addr col ad +1 col ad +2 ma[9:8] sa[7:0] nras ncas dreq ndack sdbus nrd nwr tc
smsc ds ? PPC34C60 page 57 rev. 06/01/2001 advanced information 8.1 dma transfer cycle timing dma transfer type (peripheral bus <--> dram) dma transfer cycle dma transfer rate peripheral bus width dram width 8 8 1,333 [16 bclk] 750 kb/s 8 4 1,583 [19 bclk] 631,578 kb/s 16 16 1,333 [16 bclk] 1.5 mb/s 16 8 1,583 [19 bclk] 1.263 mb/s 16 4 2,083 [25 bclk] 960 kb/s figure 28 ? reset timing parameter min typ max units t1 reset pulse width 84 [2 sclk] ns figure 29 - clock timing parameter min typ max units t1 clock period (max sclk=25mhz) 40 41.67 ns t2 clock active high or low 14 ns tr clock rise time (vin = 0.4 to 3.0 v) 5 ns tf clock fall time (vin = 3.0 to 0.4 v) 5 ns nreset t1 t1 t2 t2 xin (sclk)
smsc ds ? PPC34C60 page 58 rev. 06/01/2001 advanced information figure 30 - 100 pin qfp package outlines 0.10 -c- h a a1 a2 td/te 0 l1 l e1 e d1 d e w dim a a1 a2 d d1 e e1 h l l1 e 0 w td(1) te(1) td(2) te(2) min 2.80 0.1 2.57 23.4 19.9 17.4 13.9 0.1 0.65 1.8 max 3.15 0.45 2.87 24.15 20.1 18.15 14.1 0.2 0.95 2.6 min .110 .004 .101 .921 .783 .685 .547 .004 .026 .071 max .124 .018 .113 .951 .791 .715 .555 .008 .037 .102 0 .2 21.8 15.8 22.21 16.27 12 .4 22.2 16.2 22.76 16.82 0.65 bsc 0 .008 .858 .622 .874 .641 12 .016 .874 .638 .896 .662 .0256 bsc notes: 1) coplanarity is 0.100mm (.004") maximum. 2) tolerance on the position of the leads is 0.200mm (.008") maximum. 3) package body dimensions d1 and e1 do not include the mold protrusion. maximum mold protrusion is 0.25mm (.010"). 4) dimensions td and te are important for testing by robotic handler. only above combinations of (1) or (2) are acceptable. 5) controlling dimension: millimeter. dimensions in inches for reference only and not necessarily accurate. millimeters inches

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